1. Field of the Invention
The present invention relates to a digital-to-analog (D/A) converter, and more particularly to a current cell matrix type of D/A converter for calibrating the current value of a current source cell.
2. Description of the Background Art
Conventionally, there is a type of digital-to-analog (D/A) converter having a plurality of current source cells arranged in a matrix to receive digital data to be converted to analog data through a row decoder and a column decoder. This type of D/A converter is able to convert the current value, differential-outputted from each current source cell, to an output voltage by output end resistors to deliver the resultant output voltage as an analog output.
The current source cells operate as current sources to generate cell currents in proportion to a preset bias voltage and to differential-output the resultant cell currents in response to the input codes derived from digital data. Each current source cell includes a transistor, operating as a current source, and two current source switches, respectively controlling the positive and negative outputs of the cell current. These switches are actuated in accordance with the input codes.
Thus, the amount of current flowing through the output end resistors of the D/A converter is varied by the current source switch of each current source cell.
The transistors for each current source cell may involve unevenness caused by variation in manufacturing process to generate the current value involving an error. Such an error of the current should be corrected. For example, Hsin-Hung Chen, et al., “A 14-b 150MS/s CMOS DAC with Digital Background Calibration” 2006 Symposium on VLSI Circuits Digest of Technical Papers, proposes a digital background self-calibration scheme of the CMOS DAC (Complementary Metal-Oxide Semiconductor Digital-to-Analog Converter). In this scheme, a current source for correction, such as a dummy current source cell (CAL_DAC), is provided in a current source cell, such as a digital background calibrating current source cell, to adjust the cell current.
In this scheme, the D/A converter carries out calibration for determining the correction value of the current source for correction. During the process of the calibration, each current source cell generates current to output the resultant current via a calibration switch provided on the correction path. In the D/A converter, the current value in each current source cell is converted to a corresponding analog voltage value by a resistive current-to-voltage converter. The analog voltage value is converted to corresponding digital data by a ΔΣ modulator and a digital counter. On the basis of the result of the digital-conversion, a calibration decision circuit calculates a digital value to be delivered to the current source for correction, i.e. the correction value, and causes the calculated correction value to be stored in a memory.
A D/A converter disclosed by Japanese patent laid-open publication No. 289450/1997 operates in accordance with a segment system in which D/A converted outputs of upper bit segments equalized in current value are summed to D/A converted outputs of lower bit segments weighted in current to produce an resultant analog output. To the upper bit segments, a least one segment is added, the voltage value for switching which and the region for outputting the lower bits are controlled to correct an error in that segment.
Such conventional D/A converters use the calibration technique for ameliorating its accuracy to correct the current value of the current source cells. However, the effect brought by the connections for calibration, i.e. circuit paths for correction, is not taken into account.
For example, in the constitution for calibration as disclosed by the above Hsin-Hung Chen, et al., the CMOS DAC is provided with two switches for current source outputting and one switch for calibration for a transistor operating as a current source. However, the switches thus connected in the CMOS DAC cause the capacitance additive in a node of the switch for the current source to be increased. For example, when the switch for calibration is turned on in operation for calibration and off in regular operation, the parasitic capacitance by the switch for calibration is additively caused in the course of regular operation.
Thus, in a current source cell, when large parasitic capacitance is caused additively on the node of the switch for the current source, the effect of capacitance mismatch between the cells increases to deteriorate alternating current characteristics of the D/A converter.
If the number of switches in the current source cell is increased in order to prevent deterioration of the alternating current characteristics of the D/A converter, then the circuit is increased in size.